The invention relates to a MOS memory unit for serial information processing having a first and second transfer element, with these two transfer elements being connected via a first inverter stage and with a second inverter stage being connected behind the second transfer element, and having an EEPROM cell which has a floating gate transistor and a READ transistor, with the drain electrode of the floating gate transistor being connected to the output of the first transfer element and to the input of the first inverter stage. FIG. 1 shows a known MOS memory unit of this type for serial information processing that represents a shift register cell into which data can be read in via an EEPROM cell. This shift register stage comprises in known manner two transfer elements TG1 and TG2 and two inverter stages INV1 and INV2, which are connected in series as shown in FIG. 1, with the input IN of the first transfer element TG1 representing the data input and the output OUT of the second inverter stage INV2 the data output. A further transfer element TG3 is used for feedback of the data output to the circuit node K1 connecting the first transfer element TG1 to the first inverter stage INV1. This holds the data clocked into or read into this circuit node K1. The transfer elements TG1 to TG3 are designed as CMOS transmission gates, and the inverter stages INV1 and INV2 as CMOS inverters in the known manner. The first and second transmission gates TG1 and TG2 are controlled in opposing directions with the aid of the clock signals CLOCK and CLOCKB, while the third transmission gate TG3 is controlled by means of the clock signals HOLD and HOLDB.
The circuit node K1 is connected to an EEPROM cell comprising an n-channel floating gate transistor EE1 and an associated n-channel READ transistor N1. In addition, this circuit node K1 is connected via a p-channel transistor P1 to the reference potential V.sub.DD. The operating voltage source V.sub.SS supplies not only the source and substrate connection of the READ transistor N1 and the substrate connection of the floating gate transistor EE1, but also the transmission gates TG1 to TG3 and the inverter stages INV1 and INV2. The gate electrodes of the READ transistor N1 and of the floating gate transistor EE1 lead to the outside, with a READ signal being supplied to the gate electrode of this READ transistor N1 for reading out the information from the EEPROM cell.
The shift register stage with EEPROM cell according to FIG. 1 can be used for building up a shift register with n cells in which the data are serially entered into the shift register. To generate the programming voltage for the EEPROM cells, an HV (high voltage) generator is provided which is integrated with the shift register on an integrated circuit (IC). This programming voltage is supplied via the control inputs to the EEPROM cells which otherwise have the logic level.
The following is intended to explain the mode of operation of a shift register of this type, i.e. reading out of data from the EEPROM cell into a shift register stage according to FIG. 1 in conjunction with a possible read-out diagram according to FIG. 2, with the read-out operation being effected with the internal clock signal CLK shown there while the system clock signal CLOCK or CLOCKB is at logic "0" or logic "1", so that the transmission gate TG1 remains blocked during the entire read-out operation. In operation, this circuit according to FIG. 1 operates with logic levels of 0/-5 V, with the value 0 V representing logic "1" (H level) and the -5 V value logic "0" (L level). To read out the information from the EEPROM cell, a SET signal is first given according to FIG. 2 and switches the transistor P1 to conducting, with the result that the circuit node K1 is at logic level "1". Then the p-channel transistor P1 is switched to conducting with an intermediate level (not shown in FIG. 2) of the SET signal in order to generate a read-out reference current. Then a READ pulse switches the READ transistor N1 to conducting. Depending on whether the floating gate transistor EE1 is programmed with a logic "1" (i.e. corresponding to a positive threshold value voltage) or with a logic "0" (corresponding to a negative threshold value voltage), this floating gate transistor EE1 blocks or conducts. If this floating gate transistor EE1 remains blocked, the circuit node K1 remains at the logic "1" level, whereas in the other case, i.e. when the floating gate transistor EE1 is conducting, the circuit node K1 is pulled to the level of the operating voltage V.sub.SS, i.e. to the level of the logic "0". Then the logic level read out at the circuit node K1 is fed back to the circuit node K1 by the HOLD or HOLDB signal by means of the transmission gate TG3 and the information is hence stored in the shift register. Since all EEPROM gate electrodes of a shift register cell of this type have the same potential, the drawback is that complete programming necessitates two programming cycles. In the first programming cycle, all EEPROM gate electrodes are set to the logic "1" level, i.e. to 0 V, and at the same time the input voltage V.sub.SS is pulled to the -18 V programming voltage generated with an HV generator. The result of this is that all floating gate transistors EE1 of which the drain electrodes are at -18 V are written and therefore programmed with a logic "1". In a second programming cycle, all EEPROM gate electrodes are supplied with the -18 V programming voltage. All floating gate transistors of which the drain electrodes are at the logic "1" level, i.e. 0 V, are now erased.
There are of course applications that only permit a low power intake from the operating voltage supply. For example, an external capacitor, which may have been charged only by a solar cell previously, can be used as the operating voltage supply for an EEPROM IC of this type.
Power input depends partly on the programming time and on the necessary current for programming. In particular, the necessary charge quantity increases if several programming steps are necessary for programming of all EEPROM cells.